网站首页 | 技术文章 | 解决方案 | 电子书籍 | 下载中心 | 电子商城 | 技术论坛 | 电子博客 | 商务信息  
联系站长
加入收藏
会员登陆
交易首页 最新信息 - 推荐信息 - 热门信息 - 免费发布 - 行业新闻 - 行业资讯 - 行业知识 - 积分说明 - 信息分类 - 企业展示 - 帮助
 您的位置: 中国电子设计 >> 解决方案 >> 工业控制 >> 正文 商务信息栏目开通公告  [2008-05-19 11:47:00]
   □  DS32EL0421、DS32ELX0421低抖动LVDS并串转换芯片应用方案   3星级
DS32EL0421、DS32ELX0421低抖动LVDS并串转换芯片应用方案
[作者:未知    转贴自:NS    点击数:    更新时间:2008-5-29
【字体:
NS公司的DS32EL0421/ DS32ELX0421是低抖动LVDS 并串转换芯片,而DS32EL0124/DS32ELX0124则是串并转换芯片.这种SERDES芯片组具有高达5个并行输入的LVDS通路,数据速率高达3.125Gbps,而在3.125Gbps时的本征抖动为35ps. SERDES芯片组广泛应用在图像和显示器,视频传输,通信系统,测试和测量设备以及工业总线.本文介绍了SERDES芯片组的主要特性,关键的指标,典型应用以及典型的接口电路.

The DS32EL0421/DS32ELX0421 is a 125 MHz to 312.5 MHz (DDR) serializer for high-speed serial transmission over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface.
The DS32EL0421/DS32ELX0421 serializes up to 5 parallel input LVDS channels to create a maximum data payload of 3.125 Gbps. If the integrated DC-balance encoding is enabled, the maximum data payload achievable is 2.5 Gbps.
The DS32EL0421/DS32ELX0421 serializers feature remote sense capability to automatically detect and negotiate link status with its companion
DS32EL0124/DS32ELX0124 deserializers without requiring an additional feedback path.
The parallel LVDS interface reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.
The DS32EL0421/DS32ELX0421 is programmable through a SMBus interface as well as through control pins.
主要特性:
■ 5-bit LVDS parallel data interface
■ Programmable transmit de-emphasis
■ Configurable output levels (VOD)
■ Selectable DC-balanced encoder
■ Selectable data scrambler
■ Remote Sense for automatic detection and negotiation of link status
■ On chip LC VCOs
■ Redundant serial output (ELX device only)
■ Data valid signaling to assist with synchronization of multiple receivers
■ Supports AC- and DC-coupled signaling
■ Integrated CML and LVDS terminations
■ Configurable PLL loop bandwidth
■ Programmable output termination (50Ω or 75Ω).
■ Built-in test pattern generator
■ Loss of lock and error reporting
■ Configurable via SMBus
■ 48-pin LLP package with exposed DAP



关键的指标:
■ 1.25 to 3.125 Gbps serial data rate
■ 125 to 312.5 MHz DDR parallel clock
■ -40° to +85°C temperature range
■ >8 kV ESD (HBM) protection
■ Low Intrinsic Jitter — 35ps at 3.125 Gbps
目标应用:
■ Imaging: Industrial, Medical Security, Printers
■ Displays: LED walls, Commercial
■ Video Transport
■ Communication Systems
■ Test and Measurement
■ Industrial Bus



图1.典型应用



图2. DS32ELX0421典型的接口电路
  • 上一篇文章:TAS3308用于音频片上系统方案
  • 下一篇文章:没有了
  • Google
     
    Web www.cediy.com
    发表评论 □告诉好友 □打印此文 □关闭窗口
     最新热点文章

  • 没有任何方案
  •  
     最新推荐文章

  • 没有任何方案
  •  
     相 关 文 章
      ◇  网友评论:(只显示最新5条。评论内容只代表网友观点,与本站立场无关!)
     设为首页  加入收藏  关于本站  版权申明   联系站长   宣传赚点   友情链接
    如果我在线,不用加为好友,立刻与我交谈。 业务咨询QQ:342488946
    Copyright© 2004-2010 CEDIY.COM .All Rights Reserved
    粤ICP备05119258号